Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures

This paper presents an investigation of Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using various architectures of the Inverse Discrete Cosine Transform (IDCT). To compare FPGA architectures of different vendors, a generic FPGA model is developed and used in architecture independent modelling software. LUTs with three inputs yield the best results in terms of area when mapping the IDCT architectures to LUTs of different sizes. After placing and routing, FPGAs with a granularity of eight or sixteen LUTs and flipflops per logic block were most efficient in terms of area and